The present invention relates to digital communications, and more particularly, to synchronization of parallel data transmitted over multiple serial channels.
The data rate of a stream of parallel data may exceed the serial data rate capacity of many existing telecommunications carrier channels. Accordingly, multiple serial channels are used to accommodate the higher parallel data rate. For example, synchronized serial digital data transmission channels such as those based on the SONET standard, may provide several serial channels that are frequency locked. However, each serial channel uses a separate optical fiber so each channel may have differing time delays, wander or the like for each of the serial channels. Thus, even though the serial channels are frequency locked, the individual channels have varying phase, jitter and skew. Accordingly, the digital data must be resynchronized at the receiving end. Existing systems generally resynchronize the digital data using high speed digital circuits operating at the serial data rate. Also, the digital circuits often includes complicated smoothing or averaging circuits for reducing jitter and the like.
Accordingly, there exists a need for a data resynchronization technique that is economical and that can operate using digital circuitry operating at a clock speed that is a fraction of the serial data rate. The present invention satisfies these needs and provides further related advantages.
The present invention is embodied in an apparatus, and related method, for synchronizing parallel digital data transmitted across a plurality of serial data channels. The apparatus includes a plurality of regenerators, a clock tree and a plurality of FIFO buffers each associated with a regenerator. The plurality of regenerators receive serial data from the plurality of serial data channels, respectively. The FIFO buffers are optimized for jitter. Each regenerator generates parallel data and a data clock based on the serial data from the respective serial data channel. The clock tree generates a synchronous clock for synchronizing the parallel data. Each FIFO buffer stores the respective parallel data based on the respective data clock. The parallel data is read from the FIFO buffer based on the synchronous clock.
In more detailed features of the invention, each FIFO buffer includes a data store, a synchronous repetitive counter, a demultiplexer, a data repetitive counter and a multiplexer. The data store has a plurality of parallel data locations for storing the parallel data in response to a location select signal and for writing the parallel data in response to a write select signal. The synchronous repetitive counter generates a synchronous count for incrementally selecting each data location based on the synchronous clock. The demultiplexer is coupled between the synchronous counter and the plurality of storage locations for enabling a selected location to store the parallel data using the select signal which is generated by the demultiplexer based on the synchronous count. The data repetitive counter generates a data count for incrementally selecting each data location based on the data clock. The multiplexer is coupled between the data counter and the plurality of storage locations for reading the parallel data of a data location selected based on the data count. The synchronous counter is configured to count about 180 degrees out of phase with the count of the data counter in the absence of jitter between the synchronous clock and the data clock so that the synchronizing apparatus is optimized for jitter.
Other features and advantages of the present invention should become apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention.